1. Field of the Invention
The present invention relates to a memory device having a memory unit in which an electric charge discharging rate between two electrodes is different in accordance with the logic of stored information and a method of reading the memory device.
2. Description of the Related Art
Non-volatile memory devices that read out a difference in the discharge rate by applying a precharge voltage to a bit line are known.
As a representative example of the non-volatile semiconductor memory device to which such a reading method can be applied, there is an (flash) EEPROM.
On the other hand, in order to replace an FG-type (flash) EEPROM, as non-volatile memory devices that can rewrite data at a high speed, variable resistance-type memory devices have attracted attention.
As variable resistance-type memory devices, so-called ReRAMs are known in which a change in the resistance at the time of the input/output of conductive ions to/from a conductive film disposed within a memory unit is associated with a memory state (for example, see K. Aratani, etc. “A Novel Resistance Memory with High Scalability and Nanosecond Switching”, Technical Digest IEDM 2007, pp. 783-786).
In order to assure the reliability of rewriting characteristics, maintaining characteristics, and the like of the ReRAM and in order to apply the ReRAM further to a multiple-valued memory, as in a general flash memory or the like, a method in which a verify•read operation is performed at the time of a write operation or an erase operation is reviewed (for example, see JP-A-2009-26364, JP-A-2002-260377, and JP-A-2005-510005).
In the control of a current that is performed when a verify•read operation of a general flash memory is performed, a reading current (sense current) is approximately constant. Accordingly, by changing the electric potential of the gate of a memory transistor, a different threshold is verified. This operation method has the following merit. According to the operation method, the operating current is constant, and accordingly, the sense timing, the load of the sense node, and the like are hardly dependent upon a threshold to be verified.
A technology in which a replica cell that emulates a memory cell is used for generating a control signal in response to the timing of the operation of a memory cell is known (see Japanese Patent No. 4044538, U.S. Pat. No. 6,061,286, and T. Suzuki, etc. “0.3 to 1.5V Embedded SRAM with Device-Fluctuation-Tolerant Access-Control and Cosmic-Ray-Immune Hidden-ECC Scheme”, ISSCC 2005/SESSION 26/STATIC MEMORY/26. 6, IEEE 2005).
Such documents relate to implementation of high-speed code writing or low power consumption of an ECC circuit using timing control on the basis of a replica cell.